refactor: 模块解耦

This commit is contained in:
JiajunLI
2026-03-04 15:35:57 +08:00
parent c97ff111fa
commit 85bcbe4529
5 changed files with 298 additions and 268 deletions

16
config.py Normal file
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import os
from pathlib import Path
BASE_DIR = Path(__file__).resolve().parent
USER_DB_PATH = BASE_DIR / "users.db"
MODEL_CALL_TIMEOUT_SECONDS = 45
ASR_LANGUAGE = "zh-CN"
MODEL_NAME = os.getenv("VLM_MODEL", "Qwen/Qwen3-VL-8B-Instruct")
MODEL_BASE_URL = os.getenv("VLM_BASE_URL", "http://220.248.114.28:8000/v1")
MODEL_API_KEY = os.getenv("VLM_API_KEY", "EMPTY")
# edge-tts Yunxi 音色
TTS_VOICE = os.getenv("TTS_VOICE", "zh-CN-YunxiNeural")